The present invention relates to integrated circuits.
As integrated circuits are scaled to smaller and smaller geometry, tremendous economic pressure is placed on circuit layout techniques. That is, any modification which will permit the same circuit to be laid out smaller, for essentially the same geometries and processing conditions, will improve yield in two ways: First, if the area for each chip which is susceptible to random defects is reduced, the percentage of chips which are knocked out by random defects will presumably be reduced. Second, as area is reduced, more chips can be built on a single wafer, i.e. more chips can be built for essentially the same cost.
However, in the prior art, one factor which has continually degraded layout density is the geometry of the metallization layers, and particularly the geometry of metallization layers where contacts are necessary. FIG. 1 shows an example of the difficulties of the prior art in this respect. FIG. 1 shows a sample of a miniumum geometry layout with two metal lines 10 running parallel to each other. Each metal line 10 has width equal to the minimum geometry lambda ("lambda" is a term used by circuit designers to refer to the minimum geometry available to them in a particular process, which might be 5 microns for one set of processing conditions or 11/2 microns for another set. The particular value of lambda is relatively unimportant to the circuit designer, since he can simply state all dimensions in terms of lambda, and let the processing engineers worry about improving lambda as their process control improves.) However, FIG. 1b shows an example of what happens to the minimum geometry layout of FIG. 1a if adjacent contacts 12 are necessary. Such adjacent contacts are very frequently necessary in memory cell or microprocessor or random logic layouts. The contact holes 12 are patterned by a different patterning step (a different mask level) than the patterning of the metal lines 10, so it is possible that the locations of the contact holes 12 may be misaligned with the respect of the metal lines 10. Where the minimum geometry is lambda, the registration tolerance, i.e., the maximum amount of misalignment to be expected between structures which are, like these patterned in two different patterning steps, might typically be one quarter of lambda. Thus, if, using prior art techniques, we attempted to make both the contacts 12 and the metal lines 10 overlying them of minimum geometry, the metal lines 10 would frequently be misaligned somewhat with the contacts 12. This can have a number of undesirable effects. For example, the contact resistance will be uncontrolled, since the actual electrical area of each contact will be variable. Moreover, where contact is being made to moat or polysilicon levels, the overetch necessary to clear filaments of metal will attack these sensitive regions. Perhaps the most important disadvantage arises in via fabrication, e.g. where contact is being made from second metal to first metal or from first metal to poly: in this case, if the contact is misaligned to the edge of the lower conductor which is supposed to be contacted, the contact etch will excavate a void in the insulator adjacent to the second conductor. In this case, some of the metal subsequently deposited will be used to fill up this void, so that the metal overlying this void will be excessively thin. This provides inferior metal step coverage at these locations, so that the device may initially fail due to a open circuit, or may fail prematurely in use due to electromigration. To avoid this, in the prior art, it is necessary to widen the metal lines 10 by one registration tolerance where they cross over the contacts 12. This is the conventional layout technique shown in FIG. 1b. Note that, where no contacts are necessary, both the metal line width and the space between lines are minimum dimension lambda, so that the total pitch (i.e. the center-to-center spacing of metal lines) is merely twice lambda. Where contacts are necessary, as in FIG. 1b, the space in between the lines 10 is still minimum geometry lambda, but, at one point along their travel, the metal lines are both 11/2 times lambda wide, so that the center to center spacing of these parallel metal lines must be 21/2 times lambda. Thus, the layout density at the metal level has been very substantially degraded.
These problems apply not only to metal to moat contacts, but also to metal to poly and metal to metal contacts (commonly referred to "vias"). Heretofore, it has been desirable that the edge of a metal line should not overlap the contact which that metal line is supposed to make contact to. Again, if the metal lines must be widened to avoid missing the contact locations; then the density of the second metal layer will be degraded, and the density of the first metal layer is also likely to be degraded.
The foregoing has described the shortcomings of the prior art on the assumption that contacts can be patterned using the minimum feature size lambda. Of course, if the minimum geometry for the contacts is larger than the minimum geometry for the metal layer, which is quite likely, then the degradation imposed by the prior art as discussed above is even worse.
Thus, the foregoing problem is particularly acute in gate array and semicustom logic layouts. That is, in conventional layout techniques, a great deal of hand-optimization will typically be used to avoid having contacts lined up side by side, to mitigate the adverse affects of these contacts on metal geometry. However, where a layout is designed to be adapted, in accordance with the customer's requirements, by selectively defining the contact and second metal stages for each small quantity of circuits, the problem is even worse. This is, in designing circuits for such use it is necessary not merely to minimize adjacent location of contacts, but to minimize the collocation of possible contact locations.
Thus, if a fabrication technology could avert this necessary for minimum geometry metal lines to be widened in the neighborhood of contacts, layout problems would obviously be greatly simplified.
Thus it is an object of the present invention to provide an integrated circuit fabrication technology wherein minimum geometry metal lines need not be widened, where they intersect contact locations, to width greater than that of the contact itself.
It is a further object of the present invention to provide integrated circuit structures wherein the pitch of the metal levels is not greater than twice the minimum geometry.
It is a further object of the present invention to provide an integrated circuit fabrication process wherein metal lines crossing contact locations need not be patterned to a width any greater than the patterned width of the contact location.
To achieve these and other objects, the present invention teaches use of a sidewall in the patterned contact locations to narrow the contact by an amount equal to or greater than the registration tolerance. That is, after the contact holes have been patterned and etched, they are narrowed using a filament sidewall, so that misalignment will not cause the contacts to slop over the edge of the patterned layer which they are supposed to hit. This means that, for patterning purposes, the patterned width of the contact can be made exactly equal to the minimum geometry, and the metal level which must align with that contact can also be patterned exactly equal to the minimum geometry, without any danger of its missing the contact hole location.
According to the present invention there is provided:
A process for fabricating integrated circuits, comprising the steps of:
providing a substrate having semiconductor active device regions near the surface thereof; providing an insulating layer above predetermined portions of said active device regions;
defining a first metal interconnect layer which interconnects predetermined portions of said active device regions to configure a predetermined circuit function;
providing an interlevel dielectric above said first metal interconnect layer, and anisotropically etching said interlevel dielectric to expose said first metal interconnect layer at predetermined via locations;
conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and
depositing and patterning an additional layer of conductive material, to interconnect said via areas in a predetermined pattern.